The invention relates to the field of very low-power comparison devices, and, more particularly, to electronic equipment (e.g. battery powered electronic equipment) where the power consumed is limited. Comparison devices with very low consumption are used especially in the biomedical field, and in portable equipment or sensors.
In these fields, the electronic equipment must consume as little power as possible because the total current available is very limited. One microampere corresponds to an available order of magnitude. When it is sought to reduce the consumption of an electronic device, its performance characteristics are generally reduced. This is especially the problem with comparison devices. To reduce their consumption, it is sought to reduce the bias current. But the more this current is reduced, the lower the efficiency of the comparison devices, i.e. their switching becomes very slow. For example, a standard prior art comparator, biased at 60 microamperes, switches over in about a hundred nanoseconds. When biased at 500 nanoamperes it will switch over in six microseconds.
A standard comparator usually has at least two gain stages and one output stage used for the reshaping of the output signal, which includes a sequence of inverters. A comparator of this kind has dissymmetrical behavior in switching. It switches over more quickly in one direction than in another. This dissymmetry in switching is aggravated at very low bias current.
FIG. 1 shows a prior art comparator used to compare two signals MI and PI applied to the input. In general, one of the two signals is a reference signal. In the example, and as shown in FIG. 2, the signal MI is the reference signal with a level supposed to be constant and the signal PI is a signal with a variable level, given by an unspecified measurement circuit that is not shown. The signal MI is applied to the non-inverting input e+ and the signal PI is applied to the inverting input exe2x88x92.
The comparator is powered by the two logic supply voltages VPLUS and VMINUS with VPLUS greater than VMINUS. In practice, VPLUS has a value between 2 and 5 volts depending on the technology used and VMINUS is equal to zero volts. In the example, the comparator comprises two gain stages ED1 and EA1. The gain stage E1 is the input stage of the comparator. At the inputs e+ and exe2x88x92, it receives the two signals to be compared, MI and PI. To each input, there corresponds an arm of the stage. The first arm is associated with the non-inverting input e+. It comprises two transistors M1 and M2 series-connected between the power voltage VPLUS and a bias node N. The transistor M1, in the example, is a P type MOS transistor diode-mounted with the gate and drain connected together. The transistor M2 in one example is an N type MOS transistor. Its gate forms the non-inverting input e+ receiving the input signal M1.
The second arm is associated with the inverting input exe2x88x92. It has two transistors M3 and M4 that are series-connected between the supply voltage VPLUS and the bias node N. The transistor M3, in the example, is a P type MOS transistor with its gate connected to the gate of the transistor M1 of the first arm (current mirror assembly). The transistor M4 is an N type MOS transistor. Its gate forms the inverting input exe2x88x92 receiving the input signal PI.
This input stage is biased by a bias current Ib generally given by a current mirror structure that comprises a transistor M5 connected between the bias node N and the supply voltage VMINUS. The connection point between the transistor M3 and the transistor M4 gives the output signal of the stage applied to the input E1 of the second gain stage EA1. The signal at input E1 is such that, when the signal level PI becomes lower than that of the signal MI, it rises to xe2x80x9c1xe2x80x9d and when the level of the signal PI becomes greater than that of MI, it falls below xe2x80x9c0xe2x80x9d.
The second gain stage comprises, in the example, a first transistor M6 biased by the bias current Ib. In the example, this current is a P type MOS transistor whose drain gives the output signal OUT1 of the comparator. When the input El rises to xe2x80x9c1xe2x80x9d (PI less than MI), the transistor M6 is off and the output OUT1 falls to xe2x80x9c0xe2x80x9d. So that the transistor M6 may be off, its gate which is connected to the input E1 should be brought from zero (VMINUS) to a potential higher than or equal to VPLUS-Vtp, Vtp being the threshold voltage of a P type MOS transistor. The output OUT1 then falls to zero (VMINUS), discharged by the bias current Ib. FIG. 1 shows the charging capacitance at output which corresponds to the gate capacitances of the inverters of the output stage (not shown).
When the input El falls to xe2x80x9c0xe2x80x9d (PI greater than MI), the transistor M6 is on, drawing the output OUT1 to xe2x80x9c1xe2x80x9d. Now the transistor M6 comes on as soon as the input E1 goes from VPLUS to VPLUS-Vtp. The output transistor M6 is furthermore sized to facilitate the build-up of the output OUT1 to VPLUS. 
Thus, it can be seen that the switch-over in the comparator which corresponds to the change-over of the output OUT1 from xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d is very fast because of the sizing of the transistor M6 in combination with the small variation in charge of the node E1 (from VPLUS to VPLUS-Vtp) needed to start making the transistor M6 come on.
The switch-over of the comparator which corresponds to the change-over of the output OUT1 from xe2x80x9c1xe2x80x9d to xe2x80x9c0xe2x80x9d is slower because of the greater variation in charge (from 0 to VPLUS-Vtp) on the node E1 needed to be able to turn the transistor M6 off. Furthermore, the discharging of the output node OUT1 from VPLUS to zero (VMINUS) depends on the bias current Ib. Since it is sought to have a very low bias current, this switching over is very slow in practice.
Thus, a prior art comparator has behavior that is asymmetrical in switching, aggravated by its low bias current.
FIG. 2 shows the progress of the output as a function of the level of the input signal PI as compared with the input signal MI taken as a reference, when the comparator is biased at a low bias current Ib in the range of 100 nanoamperes. When the input signal PI rises above the reference input signal MI, there is a fast build-up in voltage at the output OUT1. when the level of the signal PI returns below the input signal MI, there is first a plateau before the voltage falls back. This plateau is due to the double constraint of the build-up of the node E1 from 0 to VPLUS-Vtp and the discharging of the output OUT by a low bias current.
According to the invention, this technical problem of slow switching, aggravated at low bias current, is addressed by applying the signals PI and MI to be compared to a second comparator but invertedly so that they switch over invertedly with respect to each other. The output of each of the comparators is looped back to the other output by a control logic such that the change-over of the output of a comparator from xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d enforces the inverse switch-over in the other comparator.
In this way, the behavior of the comparison device is symmetrized with respect to the fastest switching. The gain in switching time greatly compensates for the additional consumption due to the use of two comparators.
Preferably, and given the field of application aimed at, namely the very low-power consumption values, preferably an amplifier input stage is planned for the application of the signals to be compared at input of the two comparators.
As characterized, the invention therefore relates to a device for the comparison of the levels of two input signals MI, PI comprising a first comparator where the switching of the comparator is expressed by a change-over of the output of the comparator from a first logic state into a second logic state, and the change-over of the output from the logic state xe2x80x9c0xe2x80x9d into the other state xe2x80x9c1xe2x80x9d is faster than the change-over in the other direction. The device comprises a second comparator with an identical structure, to whose input the signals to be compared are applied invertedly so that the switching operations in the comparators are inverted, the output of each comparator is applied to an associated logic circuit capable of accelerating the inverse switching in the other comparator for a change in the output corresponding to the fastest change-over.